1. Field
The present embodiments relate to a memory controller controlling access to a semiconductor memory, and relates to a system.
2. Description of the Related Art
For improving access efficiency, many of semiconductor memories such as SDRAMs have a plurality of banks capable of independent operation. In order to access a memory cell in a semiconductor memory of this type, it is necessary to supply an activate command, a read or write command, and a precharge command. The activate command is a command for selecting a word line and latching, in a sense amplifier, data held in memory cells connected to the selected word line. The read command is a command for reading the data latched in the sense amplifier. The write command is a command for rewriting the data latched in the sense amplifier in order to write data to the memory cell. The precharge command is a command for resetting bit lines connecting the memory cells to the sense amplifier to a predetermined voltage.
Generally, a unit of data latched in a sense amplifier at a time is called a page. In a case where a memory cell stores one-bit data, the number of bits of one page equals the number of memory cells connected to one word line. To read or rewrite data latched in the sense amplifier, it is only necessary to supply a read command or a write command to a memory. On the other hand, to read or rewrite data not latched in the sense amplifier, it is necessary to supply an activate command prior to the read command or the write command. In a case where the sense amplifier is latching data of another page, it is further necessary to supply a precharge command prior to the activate command.
The state where data input/output is possible only with the read command or the write command is called page hit. On the other hand, the state where the activate command is necessary prior to the read command or the write command is called page miss. In a case where a semiconductor memory has a plurality of banks, page hit or page miss is decided for each bank.
Conventionally, in order to reduce access time, there has been proposed a method in which, when it is found that the state of a bank is page miss, a precharge operation of this bank is performed after a read operation or a write operation of another bank (for example, Japanese Unexamined Patent Application Publication No. Hei 9-237490; hereinafter, reference 1). There has also been proposed a method in which, when an activate command and a read command are supplied to a bank in response to an access request, a precharge command to a bank corresponding to a subsequent access request, if its state is page miss, is executed prior to the read command (for example, Japanese Unexamined Patent Application Publication No. 2002-342159; hereinafter, reference 2).
In the method of the reference 1, the time from the supply of the access request to the start of the access in the bank corresponding to the page miss is long. Therefore, in the entire memory including a plurality of banks, access efficiency is not improved. In the method of the reference 2, in a case where the state of the bank to be accessed next is page miss and an empty clock cycle exists, the precharge command is always inserted between the activate command and the read command in other words, the states (page hit or page miss) of the plural banks to be accessed at and after the third time are not used as a basis of the decision on whether to insert the precharge command or not. This necessitates inserting one precharge command per bank, and if there is no empty clock cycle, the precharge command cannot be inserted. As a result, access efficiency cannot be sometimes improved sufficiently.